Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning

Hung Yun Hsu, Mark Po Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Schematic visualization is important for analog circuit designers to quickly recognize the structures and functions of transistor-level circuit netlists. However, most of the original analog design or other automatically extracted analog circuits are stored in the form of transistor-level netlists in the SPICE format. It can be error-prone and time-consuming to manually create an elegant and readable schematic from a netlist. Different from the conventional graph-based methods, this paper introduces a novel analog schematic diagram generation flow based on comprehensive building block classification and reinforcement learning. The experimental results show that the proposed method can effectively generate aesthetic analog circuit schematics with a higher building block compliance rate, and fewer numbers of wire bends and net crossings, resulting in better readability, compared with existing methods and modern tools.

Original languageEnglish
Title of host publicationMLCAD 2022 - Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
PublisherAssociation for Computing Machinery, Inc
Pages43-48
Number of pages6
ISBN (Electronic)9781450394864
DOIs
StatePublished - 12 Sep 2022
Event4th ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2022 - Snowbird, United States
Duration: 12 Sep 202213 Sep 2022

Publication series

NameMLCAD 2022 - Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD

Conference

Conference4th ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2022
Country/TerritoryUnited States
CitySnowbird
Period12/09/2213/09/22

Keywords

  • analog circuit
  • building block
  • reinforcement learning
  • schematic generation
  • schematic visualization

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