Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

Shuenn Yuh Lee*, Chih Yuan Chen, Jia Hua Hong, Rong Guey Chang, Po-Hung Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in 0.35μm technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20 KHz estimated by the proposed synthesis tool is 94.19 dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03 dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256 KHz is 59.52 dB, and the HSPICE simulation result is 55.39 dB.

Original languageEnglish
Pages (from-to)347-357
Number of pages11
JournalMicroelectronics Journal
Volume42
Issue number2
DOIs
StatePublished - 1 Feb 2011

Keywords

  • Automated synthesis
  • Behavioral modeling
  • Geometric programming
  • Op-amp synthesis
  • Sigma-delta modulator
  • Transistor sizing

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