Augmenting slicing trees for analog placement

Po-Hung Lin; Bo Hao Chiang; Jen Chieh Chang; Yu Chang Wu; Rong Guey Chang; Shuenn Yuh Lee

doi:10.1109/SMACD.2012.6339416

Augmenting slicing trees for analog placement

Po-Hung Lin^*, Bo Hao Chiang, Jen Chieh Chang, Yu Chang Wu, Rong Guey Chang, Shuenn Yuh Lee

^*Corresponding author for this work

Institute of Intelligent Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

The slicing-tree representation had been proven to be very effective and efficient in optimizing floorplanning/placement and handling design/layout migration in modern system-on-chips (SoCs). However, none of the previous works introduced any symmetric-feasible condition in the slicing trees for analog device-level placement. This paper augments the slicing trees by introducing a new insertion operation and presents the symmetric-feasible conditions. Based on the augmented slicing trees and the symmetric-feasible conditions, various symmetric placements can be effectively explored during analog placement optimization.

Original language	English
Title of host publication	2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
Pages	57-60
Number of pages	4
DOIs	https://doi.org/10.1109/SMACD.2012.6339416
State	Published - 11 Dec 2012
Event	2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 - Seville, Spain Duration: 19 Sep 2012 → 21 Sep 2012

Publication series

Name	2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

Conference

Conference	2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
Country/Territory	Spain
City	Seville
Period	19/09/12 → 21/09/12

Access to Document

10.1109/SMACD.2012.6339416

Cite this

Lin, P-H., Chiang, B. H., Chang, J. C., Wu, Y. C., Chang, R. G., & Lee, S. Y. (2012). Augmenting slicing trees for analog placement. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 (pp. 57-60). [6339416] (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012). https://doi.org/10.1109/SMACD.2012.6339416

Lin, Po-Hung ; Chiang, Bo Hao ; Chang, Jen Chieh et al. / Augmenting slicing trees for analog placement. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. pp. 57-60 (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012).

@inproceedings{9896a785b8604c4f886249e2916ef8e5,

title = "Augmenting slicing trees for analog placement",

abstract = "The slicing-tree representation had been proven to be very effective and efficient in optimizing floorplanning/placement and handling design/layout migration in modern system-on-chips (SoCs). However, none of the previous works introduced any symmetric-feasible condition in the slicing trees for analog device-level placement. This paper augments the slicing trees by introducing a new insertion operation and presents the symmetric-feasible conditions. Based on the augmented slicing trees and the symmetric-feasible conditions, various symmetric placements can be effectively explored during analog placement optimization.",

author = "Po-Hung Lin and Chiang, {Bo Hao} and Chang, {Jen Chieh} and Wu, {Yu Chang} and Chang, {Rong Guey} and Lee, {Shuenn Yuh}",

year = "2012",

month = dec,

day = "11",

doi = "10.1109/SMACD.2012.6339416",

language = "English",

isbn = "9781467306867",

series = "2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012",

pages = "57--60",

booktitle = "2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012",

note = "2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 ; Conference date: 19-09-2012 Through 21-09-2012",

}

Lin, P-H, Chiang, BH, Chang, JC, Wu, YC, Chang, RG & Lee, SY 2012, Augmenting slicing trees for analog placement. in 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012., 6339416, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012, pp. 57-60, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012, Seville, Spain, 19/09/12. https://doi.org/10.1109/SMACD.2012.6339416

Augmenting slicing trees for analog placement. / Lin, Po-Hung; Chiang, Bo Hao; Chang, Jen Chieh et al.
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. p. 57-60 6339416 (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chang, Rong Guey

AU - Lee, Shuenn Yuh

PY - 2012/12/11

Y1 - 2012/12/11

N2 - The slicing-tree representation had been proven to be very effective and efficient in optimizing floorplanning/placement and handling design/layout migration in modern system-on-chips (SoCs). However, none of the previous works introduced any symmetric-feasible condition in the slicing trees for analog device-level placement. This paper augments the slicing trees by introducing a new insertion operation and presents the symmetric-feasible conditions. Based on the augmented slicing trees and the symmetric-feasible conditions, various symmetric placements can be effectively explored during analog placement optimization.

AB - The slicing-tree representation had been proven to be very effective and efficient in optimizing floorplanning/placement and handling design/layout migration in modern system-on-chips (SoCs). However, none of the previous works introduced any symmetric-feasible condition in the slicing trees for analog device-level placement. This paper augments the slicing trees by introducing a new insertion operation and presents the symmetric-feasible conditions. Based on the augmented slicing trees and the symmetric-feasible conditions, various symmetric placements can be effectively explored during analog placement optimization.

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M3 - Conference contribution

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BT - 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

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Lin P-H, Chiang BH, Chang JC, Wu YC, Chang RG, Lee SY. Augmenting slicing trees for analog placement. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. p. 57-60. 6339416. (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012). doi: 10.1109/SMACD.2012.6339416

Augmenting slicing trees for analog placement

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