Asymmetrical write-assist for single-ended SRAM operation

Jihi Yu Lin; Ming Hsien Tu; Ming Chien Tsai; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/SOCCON.2009.5398086

Asymmetrical write-assist for single-ended SRAM operation

Jihi Yu Lin^*, Ming Hsien Tu, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2009
Pages	101-104
Number of pages	4
DOIs	https://doi.org/10.1109/SOCCON.2009.5398086
State	Published - 2009
Event	IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: 9 Sep 2009 → 11 Sep 2009

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2009

Conference

Conference	IEEE International SOC Conference, SOCC 2009
Country/Territory	Ireland
City	Belfast
Period	9/09/09 → 11/09/09

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10.1109/SOCCON.2009.5398086

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@inproceedings{c96e7b2dd5254d2e99d85c4c4be85ad7,

title = "Asymmetrical write-assist for single-ended SRAM operation",

abstract = "In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.",

author = "Lin, {Jihi Yu} and Tu, {Ming Hsien} and Tsai, {Ming Chien} and Shyh-Jye Jou and Chuang, {Ching Te}",

year = "2009",

doi = "10.1109/SOCCON.2009.5398086",

language = "English",

isbn = "9781424452200",

series = "Proceedings - IEEE International SOC Conference, SOCC 2009",

pages = "101--104",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2009",

note = "IEEE International SOC Conference, SOCC 2009 ; Conference date: 09-09-2009 Through 11-09-2009",

}

Lin, JY, Tu, MH, Tsai, MC, Jou, S-J & Chuang, CT 2009, Asymmetrical write-assist for single-ended SRAM operation. in Proceedings - IEEE International SOC Conference, SOCC 2009., 5398086, Proceedings - IEEE International SOC Conference, SOCC 2009, pp. 101-104, IEEE International SOC Conference, SOCC 2009, Belfast, Ireland, 9/09/09. https://doi.org/10.1109/SOCCON.2009.5398086

TY - GEN

T1 - Asymmetrical write-assist for single-ended SRAM operation

AU - Lin, Jihi Yu

AU - Tu, Ming Hsien

AU - Tsai, Ming Chien

AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

PY - 2009

Y1 - 2009

N2 - In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

AB - In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

UR - http://www.scopus.com/inward/record.url?scp=77949609975&partnerID=8YFLogxK

U2 - 10.1109/SOCCON.2009.5398086

DO - 10.1109/SOCCON.2009.5398086

M3 - Conference contribution

AN - SCOPUS:77949609975

SN - 9781424452200

T3 - Proceedings - IEEE International SOC Conference, SOCC 2009

SP - 101

EP - 104

BT - Proceedings - IEEE International SOC Conference, SOCC 2009

T2 - IEEE International SOC Conference, SOCC 2009

Y2 - 9 September 2009 through 11 September 2009

ER -

Asymmetrical write-assist for single-ended SRAM operation

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