Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFET's

T. Y. Chan; A. T. Wu; P. K. Ko; Chen-Ming Hu; Reda R. Razouk

doi:10.1109/EDL.1986.26277

Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFET's

T. Y. Chan, A. T. Wu, P. K. Ko, Chen-Ming Hu, Reda R. Razouk

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

39 Scopus citations

Abstract

An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the 1-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive bevel angle.

Original language	English
Pages (from-to)	16-19
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	7
Issue number	1
DOIs	https://doi.org/10.1109/EDL.1986.26277
State	Published - 1 Jan 1986

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Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFET's

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