@inproceedings{f2f3c394d44d41a790f4bc933019fd69,
title = "Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application",
abstract = "Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS are employed and the capacitance mismatch due to process variation is compensated using a self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm2. The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step.",
keywords = "SAR ADC, low power, neural sensing, self-calibration",
author = "Chen, {Jr Ming} and Po-Tsang Huang and Wu, {Shang Lin} and Wei Hwang and Chuang, {Ching Te}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 29th IEEE International System on Chip Conference, SOCC 2016 ; Conference date: 06-09-2016 Through 09-09-2016",
year = "2016",
month = jul,
day = "2",
doi = "10.1109/SOCC.2016.7905425",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "18--23",
editor = "Karan Bhatia and Massimo Alioto and Danella Zhao and Andrew Marshall and Ramalingam Sridhar",
booktitle = "Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016",
address = "United States",
}