Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Ming-Dou Ker

doi:10.1109/VTSA.1997.614730

Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Ming-Dou Ker^*

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

13 Scopus citations

Abstract

A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.

Original language	English
Pages	69-73
Number of pages	5
DOIs	https://doi.org/10.1109/VTSA.1997.614730
State	Published - 1997
Event	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China Duration: 3 Jun 1997 → 5 Jun 1997

Conference

Conference	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, China
Period	3/06/97 → 5/06/97

Access to Document

10.1109/VTSA.1997.614730

Cite this

@conference{dd97b731e051410eae4b94717fa69afc,

title = "Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection",

abstract = "A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.",

author = "Ming-Dou Ker",

year = "1997",

doi = "10.1109/VTSA.1997.614730",

language = "English",

pages = "69--73",

note = "Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 03-06-1997 Through 05-06-1997",

}

TY - CONF

T1 - Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

AU - Ker, Ming-Dou

PY - 1997

Y1 - 1997

N2 - A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.

AB - A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.

UR - http://www.scopus.com/inward/record.url?scp=0030718333&partnerID=8YFLogxK

U2 - 10.1109/VTSA.1997.614730

DO - 10.1109/VTSA.1997.614730

M3 - Paper

AN - SCOPUS:0030718333

SP - 69

EP - 73

T2 - Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 3 June 1997 through 5 June 1997

ER -

Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this