A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.
|Number of pages
|Published - 1 Jan 1997
|Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 1997 → 5 Jun 1997
|Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
|3/06/97 → 5/06/97