Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

Chih Ting Yeh; Ming-Dou Ker

doi:10.1109/VLDI-DAT.2013.6533801

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

Chih Ting Yeh, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

An area-efficient power-rail electrostatic discharge (ESD) clamp circuit with silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. By modifying the layout structure, the ESD-transient detection circuit can be totally embedded in the SCR device. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 7kV human-body-model (HBM) and 350V machinemodel (MM) ESD levels under the ESD stress event, while consuming the standby leakage current in the order of nano-ampere at room temperature under the normal circuit operating condition with 1V bias.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533801
State	Published - 2013
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan Duration: 22 Apr 2013 → 24 Apr 2013

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/13 → 24/04/13

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10.1109/VLDI-DAT.2013.6533801

Cite this

Yeh, C. T., & Ker, M.-D. (2013). Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 Article 6533801 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533801

@inproceedings{d2fecaf45e9e48529bbdba301537e955,

title = "Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process",

abstract = "An area-efficient power-rail electrostatic discharge (ESD) clamp circuit with silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. By modifying the layout structure, the ESD-transient detection circuit can be totally embedded in the SCR device. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 7kV human-body-model (HBM) and 350V machinemodel (MM) ESD levels under the ESD stress event, while consuming the standby leakage current in the order of nano-ampere at room temperature under the normal circuit operating condition with 1V bias.",

author = "Yeh, {Chih Ting} and Ming-Dou Ker",

year = "2013",

doi = "10.1109/VLDI-DAT.2013.6533801",

language = "English",

isbn = "9781467344357",

series = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

note = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

}

Yeh, CT & Ker, M-D 2013, Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533801, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, 22/04/13. https://doi.org/10.1109/VLDI-DAT.2013.6533801

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. / Yeh, Chih Ting; Ker, Ming-Dou.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533801 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - An area-efficient power-rail electrostatic discharge (ESD) clamp circuit with silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. By modifying the layout structure, the ESD-transient detection circuit can be totally embedded in the SCR device. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 7kV human-body-model (HBM) and 350V machinemodel (MM) ESD levels under the ESD stress event, while consuming the standby leakage current in the order of nano-ampere at room temperature under the normal circuit operating condition with 1V bias.

AB - An area-efficient power-rail electrostatic discharge (ESD) clamp circuit with silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. By modifying the layout structure, the ESD-transient detection circuit can be totally embedded in the SCR device. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 7kV human-body-model (HBM) and 350V machinemodel (MM) ESD levels under the ESD stress event, while consuming the standby leakage current in the order of nano-ampere at room temperature under the normal circuit operating condition with 1V bias.

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M3 - Conference contribution

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Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

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