A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.
|Number of pages||3|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong|
Duration: 29 Jun 1996 → 29 Jun 1996
|Conference||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting|
|City||Hong Kong, Hong Kong|
|Period||29/06/96 → 29/06/96|