Area-efficient ESD-transient detection circuit with smaller capacitance for on-chip power-rail ESD protection in CMOS ICs

Shih Hung Chen*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    26 Scopus citations

    Abstract

    The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal-oxide-semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13-μm CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.

    Original languageEnglish
    Pages (from-to)359-363
    Number of pages5
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Volume56
    Issue number5
    DOIs
    StatePublished - 30 Apr 2009

    Keywords

    • ESD protection design
    • ESD-transient detection circuit
    • Electrostatic discharge
    • Power-rail ESD clamp circuit

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