Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Ming-Dou Ker; Kuo Feng Wang; Mei Chu Joe; Yuan Hua Chu; Tain Shun Wu

doi:10.1109/ASIC.1995.580696

Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Ming-Dou Ker^*, Kuo Feng Wang, Mei Chu Joe, Yuan Hua Chu, Tain Shun Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.

Original language	English
Article number	5218681
Pages (from-to)	123-125
Number of pages	3
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1995.580696
State	Published - 1 Dec 1995
Event	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: 18 Sep 1995 → 22 Sep 1995

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title = "Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC",

abstract = "There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.",

author = "Ming-Dou Ker and Wang, {Kuo Feng} and Joe, {Mei Chu} and Chu, {Yuan Hua} and Wu, {Tain Shun}",

year = "1995",

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doi = "10.1109/ASIC.1995.580696",

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T1 - Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

AU - Ker, Ming-Dou

AU - Wang, Kuo Feng

AU - Joe, Mei Chu

AU - Chu, Yuan Hua

AU - Wu, Tain Shun

PY - 1995/12/1

Y1 - 1995/12/1

N2 - There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.

AB - There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.

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U2 - 10.1109/ASIC.1995.580696

DO - 10.1109/ASIC.1995.580696

M3 - Conference article

AN - SCOPUS:0029543507

SN - 1063-0988

SP - 123

EP - 125

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

M1 - 5218681

Y2 - 18 September 1995 through 22 September 1995

ER -

Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

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