@inproceedings{030883babd864f35b2c8526c93781857,
title = "Architecture design of QPP interleaver for parallel turbo decoding",
abstract = "Quadratic permutation polynomial (QPP) interleaver has the advantage of contention-free for parallel memory access and has been adopted in the 3GPP LTE for turbo coding. Conventional implementations of the QPP interleaver based on the look-up table or on-line calculation usually result in large circuit area or higher clock rate for parallel turbo decoding. In this paper, an architecture design of QPP interleaver for parallel turbo decoding is presented which can provide parallel memory access without extra storage of interleaving patterns or the increment of clock rate compared with the conventional approaches. The proposed design is also reconfigurable for variable interleaver lengths.",
keywords = "Parallel decoding, QPP interleaver, Variable interleaver lengths",
author = "Lee, \{Shuenn Gi\} and Chung-Hsuan Wang and Sheen, \{Wern Ho\}",
year = "2010",
month = jul,
day = "30",
doi = "10.1109/VETECS.2010.5493793",
language = "English",
isbn = "9781424425198",
series = "IEEE Vehicular Technology Conference",
booktitle = "2010 IEEE 71st Vehicular Technology",
note = "2010 IEEE 71st Vehicular Technology Conference, VTC 2010-Spring ; Conference date: 16-05-2010 Through 19-05-2010",
}