Architectural synthesis frameworks on distributed register-file microarchitecture family

Chia I. Chen; Juinn-Dar Huang

doi:10.1109/ISVLSI.2011.19

Architectural synthesis frameworks on distributed register-file microarchitecture family

Chia I. Chen^*, Juinn-Dar Huang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, we first develop a communication synthesis framework targeting the original DRFM. The algorithm aims to optimize both interconnect resources (IIC) and system performance (latency). Then we propose a new distributed register-file based platform-DRFM-IID, where the delay model is one step toward reality. Furthermore, a dedicated synthesis framework for DRFM-IID, which focuses on minimizing the system latency and power consumption simultaneously, is also proposed. We thoroughly investigate all existing woks about distributed register-file microarchitecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.

Original language	English
Title of host publication	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages	369-370
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2011.19
State	Published - 14 Sep 2011
Event	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India Duration: 4 Jul 2011 → 6 Jul 2011

Publication series

Name	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Conference

Conference	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Country/Territory	India
City	Chennai
Period	4/07/11 → 6/07/11

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10.1109/ISVLSI.2011.19

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title = "Architectural synthesis frameworks on distributed register-file microarchitecture family",

abstract = "In this work, we first develop a communication synthesis framework targeting the original DRFM. The algorithm aims to optimize both interconnect resources (IIC) and system performance (latency). Then we propose a new distributed register-file based platform-DRFM-IID, where the delay model is one step toward reality. Furthermore, a dedicated synthesis framework for DRFM-IID, which focuses on minimizing the system latency and power consumption simultaneously, is also proposed. We thoroughly investigate all existing woks about distributed register-file microarchitecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.",

author = "Chen, {Chia I.} and Juinn-Dar Huang",

year = "2011",

month = sep,

day = "14",

doi = "10.1109/ISVLSI.2011.19",

language = "English",

isbn = "9780769544472",

series = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

pages = "369--370",

booktitle = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

note = "2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 ; Conference date: 04-07-2011 Through 06-07-2011",

}

Chen, CI & Huang, J-D 2011, Architectural synthesis frameworks on distributed register-file microarchitecture family. in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011., 5992528, Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, pp. 369-370, 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, India, 4/07/11. https://doi.org/10.1109/ISVLSI.2011.19

Architectural synthesis frameworks on distributed register-file microarchitecture family. / Chen, Chia I.; Huang, Juinn-Dar.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. 2011. p. 369-370 5992528 (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this work, we first develop a communication synthesis framework targeting the original DRFM. The algorithm aims to optimize both interconnect resources (IIC) and system performance (latency). Then we propose a new distributed register-file based platform-DRFM-IID, where the delay model is one step toward reality. Furthermore, a dedicated synthesis framework for DRFM-IID, which focuses on minimizing the system latency and power consumption simultaneously, is also proposed. We thoroughly investigate all existing woks about distributed register-file microarchitecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.

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Y2 - 4 July 2011 through 6 July 2011

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Architectural synthesis frameworks on distributed register-file microarchitecture family

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