Application of Wafer Defect Pattern Classification Model in the Semiconductor Industry

Chin Wei Lee, Daniel Hládek, Matúš Pleva, Yuan Fu Liao, Ming Hsiang Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Deep learning (DL) methods are widely employed in the semiconductor manufacturing process to enhance pattern recognition and classification accuracy, specifically for addressing defect patterns. However, the classification performance of the current models is hindered by the imbalanced distribution of defect data within the test dataset. To tackle this issue, this study presents a feature extraction approach utilizing data transformation, and ensemble learning techniques aiming to enhance the model's classification performance. The primary objective of this study is to mitigate selection and imbalance problems in the dataset through random sampling and assigning distinct weights to individual classifiers. The results demonstrate that the proposed method achieves an impressive accuracy rate of 95.09%, thus substantiating its efficacy in improving the robustness of both the classification model and wafer classification.

Original languageEnglish
Title of host publication2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2173-2177
Number of pages5
ISBN (Electronic)9798350300673
DOIs
StatePublished - 2023
Event2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023 - Taipei, Taiwan
Duration: 31 Oct 20233 Nov 2023

Publication series

Name2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023

Conference

Conference2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023
Country/TerritoryTaiwan
CityTaipei
Period31/10/233/11/23

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