Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

I. Cheng Lin; Chih Yao Huang; Chuan Jane Chao; Ming-Dou Ker; Sung Yu Chuan; Len Yi Leu; Fu Chien Chiu; Jen Chou Tseng

doi:10.1109/IPFA.2002.1025615

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

I. Cheng Lin, Chih Yao Huang, Chuan Jane Chao, Ming-Dou Ker, Sung Yu Chuan, Len Yi Leu, Fu Chien Chiu, Jen Chou Tseng

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.

Original language	English
Title of host publication	Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
Editors	Wai Kin Chim, John Thong, Wilson Tan, Kheng Chooi Lee
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	75-79
Number of pages	5
ISBN (Electronic)	0780374169
DOIs	https://doi.org/10.1109/IPFA.2002.1025615
State	Published - 2002
Event	9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 - Singapore, Singapore Duration: 12 Jul 2002 → …

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2002-January

Conference

Conference	9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
Country/Territory	Singapore
City	Singapore
Period	12/07/02 → …

Keywords

Breakdown voltage
CMOS integrated circuits
Circuit testing
Clamps
Electrostatic discharge
Pins
Power supplies
Protection
Resistors
Thyristors

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10.1109/IPFA.2002.1025615

Cite this

Lin, I. C., Huang, C. Y., Chao, C. J., Ker, M.-D., Chuan, S. Y., Leu, L. Y., Chiu, F. C., & Tseng, J. C. (2002). Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. In W. K. Chim, J. Thong, W. Tan, & K. C. Lee (Eds.), Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 (pp. 75-79). Article 1025615 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2002.1025615

Lin, I. Cheng ; Huang, Chih Yao ; Chao, Chuan Jane et al. / Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002. editor / Wai Kin Chim ; John Thong ; Wilson Tan ; Kheng Chooi Lee. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 75-79 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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title = "Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product",

abstract = "Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.",

keywords = "Breakdown voltage, CMOS integrated circuits, Circuit testing, Clamps, Electrostatic discharge, Pins, Power supplies, Protection, Resistors, Thyristors",

author = "Lin, {I. Cheng} and Huang, {Chih Yao} and Chao, {Chuan Jane} and Ming-Dou Ker and Chuan, {Sung Yu} and Leu, {Len Yi} and Chiu, {Fu Chien} and Tseng, {Jen Chou}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 ; Conference date: 12-07-2002",

year = "2002",

doi = "10.1109/IPFA.2002.1025615",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "75--79",

editor = "Chim, {Wai Kin} and John Thong and Wilson Tan and Lee, {Kheng Chooi}",

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Lin, IC, Huang, CY, Chao, CJ, Ker, M-D, Chuan, SY, Leu, LY, Chiu, FC & Tseng, JC 2002, Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. in WK Chim, J Thong, W Tan & KC Lee (eds), Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002., 1025615, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 75-79, 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002, Singapore, Singapore, 12/07/02. https://doi.org/10.1109/IPFA.2002.1025615

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. / Lin, I. Cheng; Huang, Chih Yao; Chao, Chuan Jane et al.
Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002. ed. / Wai Kin Chim; John Thong; Wilson Tan; Kheng Chooi Lee. Institute of Electrical and Electronics Engineers Inc., 2002. p. 75-79 1025615 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chiu, Fu Chien

AU - Tseng, Jen Chou

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AB - Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.

KW - Breakdown voltage

KW - CMOS integrated circuits

KW - Circuit testing

KW - Clamps

KW - Electrostatic discharge

KW - Pins

KW - Power supplies

KW - Protection

KW - Resistors

KW - Thyristors

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PB - Institute of Electrical and Electronics Engineers Inc.

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Lin IC, Huang CY, Chao CJ, Ker MD, Chuan SY, Leu LY et al. Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. In Chim WK, Thong J, Tan W, Lee KC, editors, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 75-79. 1025615. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2002.1025615

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

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