Anomalous gate-edge leakage induced by high tensile stress in NMOSFET

Po-Tsun Liu*, Chen Shuo Huang, Peng Soon Lim, Da Yuan Lee, Shueh Wen Tsao, Chi Chun Chen, Hun Jan Tao, Yuh Jier Mii

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.

Original languageEnglish
Pages (from-to)1249-1251
Number of pages3
JournalIeee Electron Device Letters
Issue number11
StatePublished - 2008


  • Gate leakage current
  • Stress memorization technique (SMT)


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