Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD

The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.