TY - GEN
T1 - Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD
AU - Lee, Jian Hsing
AU - Nidhi, Karuna
AU - Lin, Ting You
AU - Liao, Hsueh Chun
AU - Lee, Scott
AU - Ker, Ming Dou
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.
AB - The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.
KW - Electromagnetic (EM)
KW - Transmission-line Pulse (TLP)
KW - electrostatic-discharge (ESD)
UR - http://www.scopus.com/inward/record.url?scp=85140872746&partnerID=8YFLogxK
U2 - 10.1109/IPFA55383.2022.9915710
DO - 10.1109/IPFA55383.2022.9915710
M3 - Conference contribution
AN - SCOPUS:85140872746
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
BT - 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022
Y2 - 18 July 2022 through 21 July 2022
ER -