Analytical performance models for RLC interconnects and application to clock optimization

Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu Jae King, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

Original languageEnglish
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages353-357
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - 1 Jan 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: 25 Sep 200228 Sep 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Conference

Conference15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/TerritoryUnited States
CityRochester
Period25/09/0228/09/02

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