Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

Yu Chun Lee; Sekhar Reddy Kola; Chieh Yang Chen; Min Hui Chuang; Yiming Li

doi:10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

Yu Chun Lee, Sekhar Reddy Kola, Chieh Yang Chen, Min Hui Chuang, Yiming Li^*

^*Corresponding author for this work

Institute of Communications Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

Original language	English
Title of host publication	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	84-85
Number of pages	2
ISBN (Electronic)	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203692
State	Published - Aug 2020
Event	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan Duration: 10 Aug 2020 → 13 Aug 2020

Publication series

Name	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Country/Territory	Taiwan
City	Hsinchu
Period	10/08/20 → 13/08/20

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSI-TSA48913.2020.9203692

Cite this

Lee, Y. C., Kola, S. R., Chen, C. Y., Chuang, M. H., & Li, Y. (2020). Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (pp. 84-85). Article 9203692 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203692

Lee, Yu Chun ; Kola, Sekhar Reddy ; Chen, Chieh Yang et al. / Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 84-85 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

@inproceedings{078ef000cf3340888745af75dd6f0a35,

title = "Analysis of Negative Capacitance MOSFETs Characteristic with Spacer",

abstract = "In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.",

author = "Lee, {Yu Chun} and Kola, {Sekhar Reddy} and Chen, {Chieh Yang} and Chuang, {Min Hui} and Yiming Li",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203692",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "84--85",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "美國",

}

Lee, YC, Kola, SR, Chen, CY, Chuang, MH & Li, Y 2020, Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. in 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203692, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., pp. 84-85, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. / Lee, Yu Chun; Kola, Sekhar Reddy; Chen, Chieh Yang et al.
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 84-85 9203692 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

AU - Lee, Yu Chun

AU - Kola, Sekhar Reddy

AU - Chen, Chieh Yang

AU - Chuang, Min Hui

AU - Li, Yiming

PY - 2020/8

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N2 - In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

AB - In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

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M3 - Conference contribution

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BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

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Lee YC, Kola SR, Chen CY, Chuang MH, Li Y. Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 84-85. 9203692. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

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