Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

Hui Wen Tsai; Ming-Dou Ker; Yi Sheng Liu; Ming Nan Chuang

doi:10.1109/VLDI-DAT.2013.6533803

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

Hui Wen Tsai, Ming-Dou Ker, Yi Sheng Liu, Ming Nan Chuang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533803
State	Published - 15 Aug 2013
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan Duration: 22 Apr 2013 → 24 Apr 2013

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/13 → 24/04/13

Keywords

electrical overstress (EOS)
high-voltage IC
Latchup
regulator

Access to Document

10.1109/VLDI-DAT.2013.6533803

Cite this

Tsai, H. W., Ker, M-D., Liu, Y. S., & Chuang, M. N. (2013). Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 [6533803] (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533803

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title = "Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits",

abstract = "Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.",

keywords = "electrical overstress (EOS), high-voltage IC, Latchup, regulator",

author = "Tsai, {Hui Wen} and Ming-Dou Ker and Liu, {Yi Sheng} and Chuang, {Ming Nan}",

year = "2013",

month = aug,

day = "15",

doi = "10.1109/VLDI-DAT.2013.6533803",

language = "English",

isbn = "9781467344357",

series = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

note = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

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Tsai, HW, Ker, M-D, Liu, YS & Chuang, MN 2013, Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533803, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, 22/04/13. https://doi.org/10.1109/VLDI-DAT.2013.6533803

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. / Tsai, Hui Wen; Ker, Ming-Dou; Liu, Yi Sheng et al.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533803 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chuang, Ming Nan

PY - 2013/8/15

Y1 - 2013/8/15

N2 - Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.

AB - Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.

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KW - high-voltage IC

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KW - regulator

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T3 - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

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Y2 - 22 April 2013 through 24 April 2013

ER -

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

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