Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance

Shih En Huang; Shih Han Lin; Pin Su

doi:10.1109/EDTM.2019.8731312

Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance

Shih En Huang, Shih Han Lin, Pin Su

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This work analyzes and optimizes the design with emphasis on the inversion charge characteristics for InGaAs negative-capacitance FinFETs (NC-FinFETs) by using theoretical calculation corroborated with numerical simulation. Our study indicates that, optimized ferroelectric remnant-polarization (Pr) for InGaAs devices can be chosen by the capacitance matching at the optimized sub-band of the inversion capacitance. In addition, the optimized sub-band is different for the InGaAs devices with different fin-width. The P_r optimization of the InGaAs device is also different from the Si device. After the optimization, the quantum-capacitance induced inversion charge loss for InGaAs devices can be mitigated from ∼2.4X to ∼1.1X due to the action of negative capacitance.

Original language	English
Title of host publication	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	20-22
Number of pages	3
ISBN (Electronic)	9781538665084
DOIs	https://doi.org/10.1109/EDTM.2019.8731312
State	Published - Mar 2019
Event	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 - Singapore, Singapore Duration: 12 Mar 2019 → 15 Mar 2019

Publication series

Name	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019

Conference

Conference	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Country/Territory	Singapore
City	Singapore
Period	12/03/19 → 15/03/19

Keywords

CMOS
InGaAs
Negative-capacitance FET
Quantum capacitance

Access to Document

10.1109/EDTM.2019.8731312

Cite this

Huang, S. E., Lin, S. H., & Su, P. (2019). Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 (pp. 20-22). Article 8731312 (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2019.8731312

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title = "Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance",

abstract = "This work analyzes and optimizes the design with emphasis on the inversion charge characteristics for InGaAs negative-capacitance FinFETs (NC-FinFETs) by using theoretical calculation corroborated with numerical simulation. Our study indicates that, optimized ferroelectric remnant-polarization (Pr) for InGaAs devices can be chosen by the capacitance matching at the optimized sub-band of the inversion capacitance. In addition, the optimized sub-band is different for the InGaAs devices with different fin-width. The Pr optimization of the InGaAs device is also different from the Si device. After the optimization, the quantum-capacitance induced inversion charge loss for InGaAs devices can be mitigated from ∼2.4X to ∼1.1X due to the action of negative capacitance.",

keywords = "CMOS, InGaAs, Negative-capacitance FET, Quantum capacitance",

author = "Huang, {Shih En} and Lin, {Shih Han} and Pin Su",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 ; Conference date: 12-03-2019 Through 15-03-2019",

year = "2019",

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doi = "10.1109/EDTM.2019.8731312",

language = "English",

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Huang, SE, Lin, SH & Su, P 2019, Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance. in 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019., 8731312, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019, Institute of Electrical and Electronics Engineers Inc., pp. 20-22, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019, Singapore, Singapore, 12/03/19. https://doi.org/10.1109/EDTM.2019.8731312

Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance. / Huang, Shih En; Lin, Shih Han; Su, Pin.
2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 20-22 8731312 (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Huang, Shih En

AU - Lin, Shih Han

AU - Su, Pin

PY - 2019/3

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N2 - This work analyzes and optimizes the design with emphasis on the inversion charge characteristics for InGaAs negative-capacitance FinFETs (NC-FinFETs) by using theoretical calculation corroborated with numerical simulation. Our study indicates that, optimized ferroelectric remnant-polarization (Pr) for InGaAs devices can be chosen by the capacitance matching at the optimized sub-band of the inversion capacitance. In addition, the optimized sub-band is different for the InGaAs devices with different fin-width. The Pr optimization of the InGaAs device is also different from the Si device. After the optimization, the quantum-capacitance induced inversion charge loss for InGaAs devices can be mitigated from ∼2.4X to ∼1.1X due to the action of negative capacitance.

AB - This work analyzes and optimizes the design with emphasis on the inversion charge characteristics for InGaAs negative-capacitance FinFETs (NC-FinFETs) by using theoretical calculation corroborated with numerical simulation. Our study indicates that, optimized ferroelectric remnant-polarization (Pr) for InGaAs devices can be chosen by the capacitance matching at the optimized sub-band of the inversion capacitance. In addition, the optimized sub-band is different for the InGaAs devices with different fin-width. The Pr optimization of the InGaAs device is also different from the Si device. After the optimization, the quantum-capacitance induced inversion charge loss for InGaAs devices can be mitigated from ∼2.4X to ∼1.1X due to the action of negative capacitance.

KW - CMOS

KW - InGaAs

KW - Negative-capacitance FET

KW - Quantum capacitance

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M3 - Conference contribution

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Huang SE, Lin SH, Su P. Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 20-22. 8731312. (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019). doi: 10.1109/EDTM.2019.8731312

Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance

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