Analog VLSI design of cellular neural networks with annealing ability

Bing J. Sheu; Sa H. Bang; Wai-Chi  Fang

doi:10.1109/CNNA.1994.381644

Analog VLSI design of cellular neural networks with annealing ability

Bing J. Sheu^*, Sa H. Bang, Wai-Chi Fang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.

Original language	English
Pages	387-392
Number of pages	6
DOIs	https://doi.org/10.1109/CNNA.1994.381644
State	Published - 1 Dec 1994
Event	Proceedings of the 3rd IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - Rome, Italy Duration: 18 Dec 1994 → 21 Dec 1994

Conference

Conference	Proceedings of the 3rd IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94)
City	Rome, Italy
Period	18/12/94 → 21/12/94

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10.1109/CNNA.1994.381644

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title = "Analog VLSI design of cellular neural networks with annealing ability",

abstract = "Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.",

author = "Sheu, {Bing J.} and Bang, {Sa H.} and Wai-Chi Fang",

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N2 - Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.

AB - Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.

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T2 - Proceedings of the 3rd IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94)

Y2 - 18 December 1994 through 21 December 1994

ER -

Analog VLSI design of cellular neural networks with annealing ability

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