An universal VLSI architecture for bit-parallel computation in GF(2 m)

Chien Ching Lin; Fuh Ke Chang; Hsie-Chia Chang; Chen-Yi Lee

An universal VLSI architecture for bit-parallel computation in GF(2 m)

Chien Ching Lin^*, Fuh Ke Chang, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

In this paper, an universal VLSI architecture for bit-parallel computation in GF(2^m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2^m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2^m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.¹

Original language	English
Pages	125-128
Number of pages	4
State	Published - 1 Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

Cite this

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title = "An universal VLSI architecture for bit-parallel computation in GF(2 m)",

abstract = "In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1",

author = "Lin, {Chien Ching} and Chang, {Fuh Ke} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2004",

month = dec,

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An universal VLSI architecture for bit-parallel computation in GF(2 m). / Lin, Chien Ching; Chang, Fuh Ke; Chang, Hsie-Chia et al.
2004. 125-128 Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

Research output: Contribution to conference › Paper › peer-review

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N2 - In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1

AB - In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1

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An universal VLSI architecture for bit-parallel computation in GF(2 m)

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