An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang; Shien Chun Luo; Ching Ji Huang; Chih-Wei Liu; Yuan Hua Chu; Shyh-Jye Jou

doi:10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang, Shien Chun Luo, Ching Ji Huang, Chih-Wei Liu, Yuan Hua Chu, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2543-2546
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865691
State	Published - 2014
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 1 Jun 2014 → 5 Jun 2014

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	1/06/14 → 5/06/14

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISCAS.2014.6865691

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Chang, K. C., Luo, S. C., Huang, C. J., Liu, C.-W., Chu, Y. H., & Jou, S.-J. (2014). An ultra-low voltage hearing aid chip using variable-latency design technique. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 2543-2546). Article 6865691 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865691

@inproceedings{650b55cae3f8488088fda25b5cdea907,

title = "An ultra-low voltage hearing aid chip using variable-latency design technique",

abstract = "This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz",

author = "Chang, {Kuo Chiang} and Luo, {Shien Chun} and Huang, {Ching Ji} and Chih-Wei Liu and Chu, {Yuan Hua} and Shyh-Jye Jou",

year = "2014",

doi = "10.1109/ISCAS.2014.6865691",

language = "English",

isbn = "9781479934324",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2543--2546",

booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

address = "United States",

note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

Chang, KC, Luo, SC, Huang, CJ, Liu, C-W, Chu, YH & Jou, S-J 2014, An ultra-low voltage hearing aid chip using variable-latency design technique. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865691, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 2543-2546, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique. / Chang, Kuo Chiang; Luo, Shien Chun; Huang, Ching Ji et al.
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 2543-2546 6865691 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Liu, Chih-Wei

AU - Chu, Yuan Hua

AU - Jou, Shyh-Jye

PY - 2014

Y1 - 2014

N2 - This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

AB - This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

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U2 - 10.1109/ISCAS.2014.6865691

DO - 10.1109/ISCAS.2014.6865691

M3 - Conference contribution

AN - SCOPUS:84907385735

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2543

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BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

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ER -

Chang KC, Luo SC, Huang CJ, Liu CW, Chu YH, Jou SJ. An ultra-low voltage hearing aid chip using variable-latency design technique. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 2543-2546. 6865691. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique

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