An MPCN-based BCH codec architecture with arbitrary error correcting capability

Chi Heng Yang; Yi Min Lin; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/TVLSI.2014.2338309

An MPCN-based BCH codec architecture with arbitrary error correcting capability

Chi Heng Yang, Yi Min Lin, Hsie-Chia Chang, Chen-Yi Lee

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1 -24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60 -84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.

Original language	English
Article number	6876147
Pages (from-to)	1235-1244
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	23
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2014.2338309
State	Published - 1 Jul 2015

Keywords

Bose-Chaudhuri-Hocquenghem (BCH) codes
NAND flash
encoder
error correcting codes (ECC)
syndrome

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10.1109/TVLSI.2014.2338309

Cite this

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abstract = "This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1 -24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60 -84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.",

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An MPCN-based BCH codec architecture with arbitrary error correcting capability

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