An MPCN-based BCH codec architecture with arbitrary error correcting capability

Chi Heng Yang, Yi Min Lin, Hsie-Chia Chang, Chen-Yi Lee

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1 -24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60 -84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.

Original languageEnglish
Article number6876147
Pages (from-to)1235-1244
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
StatePublished - 1 Jul 2015


  • Bose-Chaudhuri-Hocquenghem (BCH) codes
  • NAND flash
  • encoder
  • error correcting codes (ECC)
  • syndrome


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