An LDPC decoder with SNR information

Kai Jiun Yang; Shang-Ho Tsai; Heng Chang Hsu

doi:10.1109/ICICS.2013.6782886

An LDPC decoder with SNR information

Kai Jiun Yang, Shang-Ho Tsai, Heng Chang Hsu

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

In this work an LDPC decoder which complies with IEEE 802.11n is proposed and implemented. The code rate is 1/2 and the code length is 648. We used partially parallel structure to reduce the area. Additionally the SNR information is applied to improve the BER performance. Moreover the CNU and the BNU in the min-sum-correct algorithm were reordered so that the hardware complexity can be reduced, and early termination can be achieved at the first iteration. Furthermore the parity check matrix is reordered such that the latency of each iteration is reduced by 1/3. The proposed LDPC decoder can reach a throughput of 37 ∼ 319Mbps with a core area of 5.3mm² and power consumption 224mW in a TSMC 90nm process.

Original language	English
DOIs	https://doi.org/10.1109/ICICS.2013.6782886
State	Published - 2013
Event	9th International Conference on Information, Communications and Signal Processing, ICICS 2013 - Tainan, Taiwan Duration: 10 Dec 2013 → 13 Dec 2013

Conference

Conference	9th International Conference on Information, Communications and Signal Processing, ICICS 2013
Country/Territory	Taiwan
City	Tainan
Period	10/12/13 → 13/12/13

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10.1109/ICICS.2013.6782886

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title = "An LDPC decoder with SNR information",

abstract = "In this work an LDPC decoder which complies with IEEE 802.11n is proposed and implemented. The code rate is 1/2 and the code length is 648. We used partially parallel structure to reduce the area. Additionally the SNR information is applied to improve the BER performance. Moreover the CNU and the BNU in the min-sum-correct algorithm were reordered so that the hardware complexity can be reduced, and early termination can be achieved at the first iteration. Furthermore the parity check matrix is reordered such that the latency of each iteration is reduced by 1/3. The proposed LDPC decoder can reach a throughput of 37 ∼ 319Mbps with a core area of 5.3mm2 and power consumption 224mW in a TSMC 90nm process.",

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year = "2013",

doi = "10.1109/ICICS.2013.6782886",

language = "English",

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AB - In this work an LDPC decoder which complies with IEEE 802.11n is proposed and implemented. The code rate is 1/2 and the code length is 648. We used partially parallel structure to reduce the area. Additionally the SNR information is applied to improve the BER performance. Moreover the CNU and the BNU in the min-sum-correct algorithm were reordered so that the hardware complexity can be reduced, and early termination can be achieved at the first iteration. Furthermore the parity check matrix is reordered such that the latency of each iteration is reduced by 1/3. The proposed LDPC decoder can reach a throughput of 37 ∼ 319Mbps with a core area of 5.3mm2 and power consumption 224mW in a TSMC 90nm process.

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DO - 10.1109/ICICS.2013.6782886

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T2 - 9th International Conference on Information, Communications and Signal Processing, ICICS 2013

Y2 - 10 December 2013 through 13 December 2013

ER -

An LDPC decoder with SNR information

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