An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

Chau-Chin Su; Po Chen Lin; Hung Wen Lu

doi:10.1109/ASSCC.2006.357852

An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

Chau-Chin Su^*, Po Chen Lin, Hung Wen Lu

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

This paper presented an inverter based 3^rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm² The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

Original language	English
Pages	63-66
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357852
State	Published - 1 Dec 2006
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357852

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abstract = "This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.",

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N2 - This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

AB - This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

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An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

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