TY - GEN
T1 - An integrated placement and routing for ratioed capacitor array based on ILP formulation
AU - Chou, Pang Yen
AU - Lin, Po-Hung
AU - Graeb, Helmut
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/31
Y1 - 2016/5/31
N2 - Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.
AB - Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.
UR - http://www.scopus.com/inward/record.url?scp=84978412131&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2016.7482535
DO - 10.1109/VLSI-DAT.2016.7482535
M3 - Conference contribution
AN - SCOPUS:84978412131
T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Y2 - 25 April 2016 through 27 April 2016
ER -