An integrated placement and routing for ratioed capacitor array based on ILP formulation

Pang Yen Chou; Po-Hung Lin; Helmut Graeb

doi:10.1109/VLSI-DAT.2016.7482535

An integrated placement and routing for ratioed capacitor array based on ILP formulation

Pang Yen Chou, Po-Hung Lin, Helmut Graeb

Institute of Intelligent Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482535
State	Published - 31 May 2016
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

Access to Document

10.1109/VLSI-DAT.2016.7482535

Cite this

Chou, P. Y., Lin, P-H., & Graeb, H. (2016). An integrated placement and routing for ratioed capacitor array based on ILP formulation. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482535] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482535

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title = "An integrated placement and routing for ratioed capacitor array based on ILP formulation",

abstract = "Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.",

author = "Chou, {Pang Yen} and Po-Hung Lin and Helmut Graeb",

year = "2016",

month = may,

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doi = "10.1109/VLSI-DAT.2016.7482535",

language = "English",

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booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

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note = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

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Chou, PY, Lin, P-H & Graeb, H 2016, An integrated placement and routing for ratioed capacitor array based on ILP formulation. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482535, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-DAT.2016.7482535

An integrated placement and routing for ratioed capacitor array based on ILP formulation. / Chou, Pang Yen; Lin, Po-Hung; Graeb, Helmut.
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482535 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chou, Pang Yen

AU - Lin, Po-Hung

AU - Graeb, Helmut

PY - 2016/5/31

Y1 - 2016/5/31

N2 - Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.

AB - Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.

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M3 - Conference contribution

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T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

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Chou PY, Lin P-H, Graeb H. An integrated placement and routing for ratioed capacitor array based on ILP formulation. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482535. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482535

An integrated placement and routing for ratioed capacitor array based on ILP formulation

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