An hardware efficient deblocking filter for H.264/AVC

Chao Chung Cheng*, Tian-Sheuan Chang

*Corresponding author for this work

    Research output: Contribution to journalConference articlepeer-review

    31 Scopus citations


    This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18μm CMOS technology. When clocked at 82.58MHz, our design can easily support real-tune deblocking of 2K×1K@30Hz video application, this high performance can meet high resolution real-time application requirement

    Original languageEnglish
    Article number6.4-1
    Pages (from-to)235-236
    Number of pages2
    JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
    StatePublished - 2005
    Event2005 Digest of Technical Papers - International Conference on Consumer Electronics, ICCE 2005 - Las Vegas, NV, United States
    Duration: 8 Jan 200512 Jan 2005


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