An event-driven incremental timing fault simulator

Shyh-Jye Jou; Wen Zen Shen; Shwu Huey Chiou

doi:10.1109/VTSA.1991.246754

An event-driven incremental timing fault simulator

Shyh-Jye Jou, Wen Zen Shen, Shwu Huey Chiou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An efficient MOS multiple sets of multiple faults simulator with electrical timing information is presented. By using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior in speedup, extra memory used and precision to other approaches. Moreover, this simulator is suited for parallel simulation in a multiprocessor system.

Original language	English
Title of host publication	1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	424-427
Number of pages	4
ISBN (Electronic)	078030036X, 9780780300361
DOIs	https://doi.org/10.1109/VTSA.1991.246754
State	Published - 1 Jan 1991
Event	1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan Duration: 22 May 1991 → 24 May 1991

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Conference

Conference	1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
Country/Territory	Taiwan
City	Taipei
Period	22/05/91 → 24/05/91

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10.1109/VTSA.1991.246754

Cite this

Jou, S-J., Shen, W. Z., & Chiou, S. H. (1991). An event-driven incremental timing fault simulator. In 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991 (pp. 424-427). Article 246754 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1991.246754

Jou, Shyh-Jye ; Shen, Wen Zen ; Chiou, Shwu Huey. / An event-driven incremental timing fault simulator. 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991. Institute of Electrical and Electronics Engineers Inc., 1991. pp. 424-427 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

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abstract = "An efficient MOS multiple sets of multiple faults simulator with electrical timing information is presented. By using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior in speedup, extra memory used and precision to other approaches. Moreover, this simulator is suited for parallel simulation in a multiprocessor system.",

author = "Shyh-Jye Jou and Shen, {Wen Zen} and Chiou, {Shwu Huey}",

year = "1991",

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doi = "10.1109/VTSA.1991.246754",

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Jou, S-J, Shen, WZ & Chiou, SH 1991, An event-driven incremental timing fault simulator. in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991., 246754, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 424-427, 1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991, Taipei, Taiwan, 22/05/91. https://doi.org/10.1109/VTSA.1991.246754

An event-driven incremental timing fault simulator. / Jou, Shyh-Jye; Shen, Wen Zen; Chiou, Shwu Huey.
1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991. Institute of Electrical and Electronics Engineers Inc., 1991. p. 424-427 246754 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - An efficient MOS multiple sets of multiple faults simulator with electrical timing information is presented. By using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior in speedup, extra memory used and precision to other approaches. Moreover, this simulator is suited for parallel simulation in a multiprocessor system.

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Jou S-J, Shen WZ, Chiou SH. An event-driven incremental timing fault simulator. In 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991. Institute of Electrical and Electronics Engineers Inc. 1991. p. 424-427. 246754. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). doi: 10.1109/VTSA.1991.246754

An event-driven incremental timing fault simulator

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