An energy-efficient switching technique for 2-bit/cycle SAR ADCs

Dune Ting Fan, Ren Hao Yeh, Yuan Sun Chu, Tsung Heng Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new energy-efficient switching technique for 2-bit/cycle successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed switching technique achieves 97.91% less switching energy and 75% less total capacitance over the conventional architecture. A LSB correction method is also proposed to relax the accuracy requirement on the comparator. The prototype was designed in a TSMC 90-nm CMOS process technology. The post-layout simulation results show that the ADC achieves a SNDR of 59.83 dB, power consumption of 0.879 mW and FoM of 10.94 fJ/conversion-step at 100 MHz sampling rate with a 1 V supply voltage.

Original languageEnglish
Title of host publication2015 9th International Symposium on Medical Information and Communication Technology, ISMICT 2015
PublisherIEEE Computer Society
Pages166-169
Number of pages4
ISBN (Electronic)9781479980727
DOIs
StatePublished - 13 May 2015
Event9th International Symposium on Medical Information and Communication Technology, ISMICT 2015 - Kamakura, Japan
Duration: 24 Mar 201526 Mar 2015

Publication series

NameInternational Symposium on Medical Information and Communication Technology, ISMICT
Volume2015-May
ISSN (Print)2326-828X
ISSN (Electronic)2326-8301

Conference

Conference9th International Symposium on Medical Information and Communication Technology, ISMICT 2015
Country/TerritoryJapan
CityKamakura
Period24/03/1526/03/15

Keywords

  • merged capacitor switching
  • successive approximation analog-to-digital converter
  • wireless sensor node

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