An energy-efficient approximate systolic array based on timing error prediction and prevention

Ning Chi Huang, Wei Kai Tseng, Huan Jan Chou, Kai Chiang Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021
PublisherIEEE Computer Society
ISBN (Electronic)9781665419499
StatePublished - 25 Apr 2021
Event39th IEEE VLSI Test Symposium, VTS 2021 - San Diego, United States
Duration: 26 Apr 202128 Apr 2021

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference39th IEEE VLSI Test Symposium, VTS 2021
Country/TerritoryUnited States
CitySan Diego


  • Approximate computing
  • Timing error prediction
  • Voltage underscaling


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