An energy-efficient approximate systolic array based on timing error prediction and prevention

Ning Chi Huang; Wei Kai Tseng; Huan Jan Chou; Kai Chiang Wu

doi:10.1109/VTS50974.2021.9441004

An energy-efficient approximate systolic array based on timing error prediction and prevention

Ning Chi Huang, Wei Kai Tseng, Huan Jan Chou, Kai Chiang Wu

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification.

Original language	English
Title of host publication	Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021
Publisher	IEEE Computer Society
ISBN (Electronic)	9781665419499
DOIs	https://doi.org/10.1109/VTS50974.2021.9441004
State	Published - 25 Apr 2021
Event	39th IEEE VLSI Test Symposium, VTS 2021 - San Diego, United States Duration: 26 Apr 2021 → 28 Apr 2021

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2021-April

Conference

Conference	39th IEEE VLSI Test Symposium, VTS 2021
Country/Territory	United States
City	San Diego
Period	26/04/21 → 28/04/21

Keywords

Approximate computing
Timing error prediction
Voltage underscaling

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VTS50974.2021.9441004

Cite this

@inproceedings{78e879f22055477c8aa3f645ba9669ee,

title = "An energy-efficient approximate systolic array based on timing error prediction and prevention",

abstract = "Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification. ",

keywords = "Approximate computing, Timing error prediction, Voltage underscaling",

author = "Huang, {Ning Chi} and Tseng, {Wei Kai} and Chou, {Huan Jan} and Wu, {Kai Chiang}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 39th IEEE VLSI Test Symposium, VTS 2021 ; Conference date: 26-04-2021 Through 28-04-2021",

year = "2021",

month = apr,

day = "25",

doi = "10.1109/VTS50974.2021.9441004",

language = "English",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

booktitle = "Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021",

address = "United States",

}

Huang, NC, Tseng, WK, Chou, HJ & Wu, KC 2021, An energy-efficient approximate systolic array based on timing error prediction and prevention. in Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021., 9441004, Proceedings of the IEEE VLSI Test Symposium, vol. 2021-April, IEEE Computer Society, 39th IEEE VLSI Test Symposium, VTS 2021, San Diego, United States, 26/04/21. https://doi.org/10.1109/VTS50974.2021.9441004

An energy-efficient approximate systolic array based on timing error prediction and prevention. / Huang, Ning Chi; Tseng, Wei Kai; Chou, Huan Jan et al.
Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 2021. 9441004 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2021-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An energy-efficient approximate systolic array based on timing error prediction and prevention

AU - Huang, Ning Chi

AU - Tseng, Wei Kai

AU - Chou, Huan Jan

AU - Wu, Kai Chiang

PY - 2021/4/25

Y1 - 2021/4/25

N2 - Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification.

AB - Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification.

KW - Approximate computing

KW - Timing error prediction

KW - Voltage underscaling

UR - http://www.scopus.com/inward/record.url?scp=85107459989&partnerID=8YFLogxK

U2 - 10.1109/VTS50974.2021.9441004

DO - 10.1109/VTS50974.2021.9441004

M3 - Conference contribution

AN - SCOPUS:85107459989

T3 - Proceedings of the IEEE VLSI Test Symposium

BT - Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021

PB - IEEE Computer Society

T2 - 39th IEEE VLSI Test Symposium, VTS 2021

Y2 - 26 April 2021 through 28 April 2021

ER -

An energy-efficient approximate systolic array based on timing error prediction and prevention

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Keywords

UN SDGs

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