This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research , this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.