An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system

Wai-Chi Fang; Jui Chung Chang; Kuan Ju Huang; Chih Wei Feng; Chia Ching Chou

doi:10.1109/BioCAS.2014.6981648

An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system

Wai-Chi Fang, Jui Chung Chang, Kuan Ju Huang, Chih Wei Feng, Chia Ching Chou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.

Original language	English
Title of host publication	IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	73-76
Number of pages	4
ISBN (Electronic)	9781479923465
DOIs	https://doi.org/10.1109/BioCAS.2014.6981648
State	Published - 9 Dec 2014
Event	10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014 - Lausanne, Switzerland Duration: 22 Oct 2014 → 24 Oct 2014

Publication series

Name	IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings

Conference

Conference	10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014
Country/Territory	Switzerland
City	Lausanne
Period	22/10/14 → 24/10/14

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10.1109/BioCAS.2014.6981648

Cite this

Fang, W.-C., Chang, J. C., Huang, K. J., Feng, C. W., & Chou, C. C. (2014). An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. In IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings (pp. 73-76). Article 6981648 (IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/BioCAS.2014.6981648

Fang, Wai-Chi ; Chang, Jui Chung ; Huang, Kuan Ju et al. / An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 73-76 (IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings).

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title = "An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system",

abstract = "This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.",

author = "Wai-Chi Fang and Chang, {Jui Chung} and Huang, {Kuan Ju} and Feng, {Chih Wei} and Chou, {Chia Ching}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014 ; Conference date: 22-10-2014 Through 24-10-2014",

year = "2014",

month = dec,

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doi = "10.1109/BioCAS.2014.6981648",

language = "English",

series = "IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings",

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Fang, W-C, Chang, JC, Huang, KJ, Feng, CW & Chou, CC 2014, An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. in IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings., 6981648, IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 73-76, 10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014, Lausanne, Switzerland, 22/10/14. https://doi.org/10.1109/BioCAS.2014.6981648

An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. / Fang, Wai-Chi; Chang, Jui Chung; Huang, Kuan Ju et al.
IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2014. p. 73-76 6981648 (IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Fang, Wai-Chi

AU - Chang, Jui Chung

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AU - Chou, Chia Ching

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N2 - This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.

AB - This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.

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Fang WC, Chang JC, Huang KJ, Feng CW, Chou CC. An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. In IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2014. p. 73-76. 6981648. (IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings). doi: 10.1109/BioCAS.2014.6981648

An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system

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