An Efficient Power Model for IP-Level Complex Designs

Chih Yang Hsu*, Chien-Nan Liu, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance (CDC) into the real power consumption of pattern pairs but still has high accuracy. In order to reduce the table size, we collect those pattern pairs with similar CDC values to be a group and only set an entry in the lookup table for each group. The proposed dynamic grouping process can automatically increase the entries of the lookup tables to cover the current CDC distribution of designs during the power characterization process. In order to improve the efficiency of characterization process, the Monte Carlo approach is used during the estimation for the average power of each group to skip the samples that will not increase the accuracy too much. After the power model of a circuit is built, the average power consumption for any test sequence can be estimated easily. The experimental result shows that the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using this lookup table.

Original languageEnglish
Pages (from-to)2073-2080
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number8
StatePublished - Aug 2003


  • Dynamic grouping
  • IP-level
  • Lookup table
  • Power model


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