In this paper, a wireless electroencephalography (EEG) acquisition analog front-end (AFE) circuit design is presented. The wireless EEG acquisition system includes an analog front-end readout chipset (AFERC) with extendable channel, a low-power MSP430 microcontroller from Texas Instruments and a commercial Bluetooth 2.0 module (BTM). The front-end readout chipset not only applies the ability of noise attenuation but also modulates the EEG signal into appropriate amplitude. It has individual 10-bit successive approximation register analog-to-digital converter (SAR-ADC) for each EEG channel, and it transmits the EEG signals which have been serially converted to digital format to MSP430. MSP430 is responsible for rearranging the converted digital bits and controlling the BTM with built-in Universal Asynchronous Receiver/Transmitter (UART) interface. The AFERC maximumly reaches to 64 channels, and single channel consumes 80.268 uW. Total power consumption of AFERC is 2.6 mW at with 32 channels, and its Common-Mode-Reject-Ratio (CMRR) is 75 dB.