An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming

Shih Hsin Hsu; Wei-Zen Chen; Jui Pin Zheng; Sean S.Y. Liu; Po Cheng Pan; Hung-Ming Chen

doi:10.1109/VLSI-DAT.2014.6834871

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming

Shih Hsin Hsu, Wei-Zen Chen, Jui Pin Zheng, Sean S.Y. Liu, Po Cheng Pan, Hung-Ming Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the 'SPICE accuracy' device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.

Original language	English
Title of host publication	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Publisher	IEEE Computer Society
ISBN (Print)	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834871
State	Published - 2014
Event	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 28 Apr 2014 → 30 Apr 2014

Publication series

Name	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Country/Territory	Taiwan
City	Hsinchu
Period	28/04/14 → 30/04/14

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10.1109/VLSI-DAT.2014.6834871

Cite this

Hsu, S. H., Chen, W.-Z., Zheng, J. P., Liu, S. S. Y., Pan, P. C., & Chen, H.-M. (2014). An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 Article 6834871 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834871

Hsu, Shih Hsin ; Chen, Wei-Zen ; Zheng, Jui Pin et al. / An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

@inproceedings{470842a4c2af41adbe4bab4311318967,

title = "An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming",

abstract = "This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the 'SPICE accuracy' device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.",

author = "Hsu, {Shih Hsin} and Wei-Zen Chen and Zheng, {Jui Pin} and Liu, {Sean S.Y.} and Pan, {Po Cheng} and Hung-Ming Chen",

year = "2014",

doi = "10.1109/VLSI-DAT.2014.6834871",

language = "English",

isbn = "9781479927760",

series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

publisher = "IEEE Computer Society",

booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

address = "美國",

note = "2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 ; Conference date: 28-04-2014 Through 30-04-2014",

}

Hsu, SH, Chen, W-Z, Zheng, JP, Liu, SSY, Pan, PC & Chen, H-M 2014, An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. in Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834871, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 28/04/14. https://doi.org/10.1109/VLSI-DAT.2014.6834871

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. / Hsu, Shih Hsin; Chen, Wei-Zen; Zheng, Jui Pin et al.
Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834871 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the 'SPICE accuracy' device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.

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Hsu SH, Chen WZ, Zheng JP, Liu SSY, Pan PC, Chen HM. An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834871. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). doi: 10.1109/VLSI-DAT.2014.6834871

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming

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