Abstract
This brief presents an area-efficient turbo decoder based on the reciprocal dual trellis. In this brief, the radix-4 structure is introduced into the reciprocal dual trellis for throughput enhancement, and a sign-arrangement technique is developed to simplify the hardware and reduce the critical path of the recursion metric unit. To further reduce the hardware complexity, a time-multiplexing method with no degradation of throughput is also presented to save half of the extrinsic units, leading to a 15% hardware reduction of the soft-in/soft-out decoder. After implementation by CMOS 90-nm process, the proposed turbo decoder containing 600 k-gates and 152-kb SRAM can achieve 425 Mb/s with 310-mW power consumption at 8/9 code rate. The post-simulation results show that the proposed methods provide a hardware-efficient solution for turbo decoders exploiting high-code-rate operations.
Original language | English |
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Article number | 6922522 |
Pages (from-to) | 65-69 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 62 |
Issue number | 1 |
DOIs | |
State | Published - 1 Jan 2015 |
Keywords
- area efficient
- high coderate
- Reciprocal dual trellis
- turbo decoder