An area-efficient parallel turbo decoder based on contention free algorithm

Kai Hsin Tseng; Hsiang Tsung Chuang; Shao Yen Tseng; Wai-Chi  Fang

doi:10.1109/VDAT.2009.5158130

An area-efficient parallel turbo decoder based on contention free algorithm

Kai Hsin Tseng^*, Hsiang Tsung Chuang, Shao Yen Tseng, Wai-Chi Fang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μim CMOS process.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	203-206
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158130
State	Published - 2009
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 28 Apr 2009 → 30 Apr 2009

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan
City	Hsinchu
Period	28/04/09 → 30/04/09

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10.1109/VDAT.2009.5158130

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Tseng, K. H., Chuang, H. T., Tseng, S. Y., & Fang, W.-C. (2009). An area-efficient parallel turbo decoder based on contention free algorithm. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 203-206). Article 5158130 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158130

@inproceedings{0e651a4402f34f208403b84e318a100f,

title = "An area-efficient parallel turbo decoder based on contention free algorithm",

abstract = "In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μim CMOS process.",

author = "Tseng, {Kai Hsin} and Chuang, {Hsiang Tsung} and Tseng, {Shao Yen} and Wai-Chi Fang",

year = "2009",

doi = "10.1109/VDAT.2009.5158130",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "203--206",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

}

Tseng, KH, Chuang, HT, Tseng, SY & Fang, W-C 2009, An area-efficient parallel turbo decoder based on contention free algorithm. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158130, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 203-206, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 28/04/09. https://doi.org/10.1109/VDAT.2009.5158130

An area-efficient parallel turbo decoder based on contention free algorithm. / Tseng, Kai Hsin; Chuang, Hsiang Tsung; Tseng, Shao Yen et al.
2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 203-206 5158130 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Fang, Wai-Chi

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N2 - In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μim CMOS process.

AB - In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μim CMOS process.

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DO - 10.1109/VDAT.2009.5158130

M3 - Conference contribution

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SN - 9781424427826

T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

SP - 203

EP - 206

BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Y2 - 28 April 2009 through 30 April 2009

ER -

An area-efficient parallel turbo decoder based on contention free algorithm

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