@inproceedings{82219aaf140e4497962fea5f0889e8f9,
title = "An area-efficient high-throughput SM4 accelerator with SCA-countermeasure for TV applications",
abstract = "The SM4 algorithm is the first commercial cipher published by China in 2012 which is widely used in WLAN WAPI resource restricted devices. This paper proposed the single-round-iterative architecture which can operate at 500 MHZ clock frequency and reach 2Gbps throughput. In order to resist side channel attack, we changed the S-box structure and add secret sharing during the computation process. According to the CPA result, this hardware is secure under the condition of collecting 1 million power traces. The gate count of this design is about 15.19k, gaining almost 17.7% area reduction to the BMTSM4 which can reach the similar throughput [1].",
author = "Wei Chiang and Chang, {Hsie Chia} and Chen-Yi Lee",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE; null ; Conference date: 10-10-2020 Through 21-10-2020",
year = "2020",
month = oct,
doi = "10.1109/ISCAS45731.2020.9180577",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",
address = "United States",
}