An area-efficient high-throughput SM4 accelerator with SCA-countermeasure for TV applications

Wei Chiang*, Hsie Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The SM4 algorithm is the first commercial cipher published by China in 2012 which is widely used in WLAN WAPI resource restricted devices. This paper proposed the single-round-iterative architecture which can operate at 500 MHZ clock frequency and reach 2Gbps throughput. In order to resist side channel attack, we changed the S-box structure and add secret sharing during the computation process. According to the CPA result, this hardware is secure under the condition of collecting 1 million power traces. The gate count of this design is about 15.19k, gaining almost 17.7% area reduction to the BMTSM4 which can reach the similar throughput [1].

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
DOIs
StatePublished - Oct 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 10 Oct 202021 Oct 2020

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
ISSN (Print)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online
Period10/10/2021/10/20

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