An area-efficient BCH codec with echelon scheduling for NAND flash applications

Chi Heng Yang; Yi Hsun Chen; Hsie-Chia Chang

doi:10.1109/ICC.2013.6655246

An area-efficient BCH codec with echelon scheduling for NAND flash applications

Chi Heng Yang, Yi Hsun Chen, Hsie-Chia Chang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.

Original language	English
Title of host publication	2013 IEEE International Conference on Communications, ICC 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	4332-4336
Number of pages	5
ISBN (Print)	9781467331227
DOIs	https://doi.org/10.1109/ICC.2013.6655246
State	Published - 2013
Event	2013 IEEE International Conference on Communications, ICC 2013 - Budapest, Hungary Duration: 9 Jun 2013 → 13 Jun 2013

Publication series

Name	IEEE International Conference on Communications
ISSN (Print)	1550-3607

Conference

Conference	2013 IEEE International Conference on Communications, ICC 2013
Country/Territory	Hungary
City	Budapest
Period	9/06/13 → 13/06/13

Access to Document

10.1109/ICC.2013.6655246

Cite this

Yang, C. H., Chen, Y. H., & Chang, H.-C. (2013). An area-efficient BCH codec with echelon scheduling for NAND flash applications. In 2013 IEEE International Conference on Communications, ICC 2013 (pp. 4332-4336). Article 6655246 (IEEE International Conference on Communications). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICC.2013.6655246

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title = "An area-efficient BCH codec with echelon scheduling for NAND flash applications",

abstract = "This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.",

author = "Yang, {Chi Heng} and Chen, {Yi Hsun} and Hsie-Chia Chang",

year = "2013",

doi = "10.1109/ICC.2013.6655246",

language = "English",

isbn = "9781467331227",

series = "IEEE International Conference on Communications",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "4332--4336",

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note = "2013 IEEE International Conference on Communications, ICC 2013 ; Conference date: 09-06-2013 Through 13-06-2013",

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Yang, CH, Chen, YH & Chang, H-C 2013, An area-efficient BCH codec with echelon scheduling for NAND flash applications. in 2013 IEEE International Conference on Communications, ICC 2013., 6655246, IEEE International Conference on Communications, Institute of Electrical and Electronics Engineers Inc., pp. 4332-4336, 2013 IEEE International Conference on Communications, ICC 2013, Budapest, Hungary, 9/06/13. https://doi.org/10.1109/ICC.2013.6655246

An area-efficient BCH codec with echelon scheduling for NAND flash applications. / Yang, Chi Heng; Chen, Yi Hsun; Chang, Hsie-Chia.
2013 IEEE International Conference on Communications, ICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 4332-4336 6655246 (IEEE International Conference on Communications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.

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An area-efficient BCH codec with echelon scheduling for NAND flash applications

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