An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory

J. P. Wu; M. Y. Lee; T. C. Kao; Y. J. Li; C. H. Liu; J. C. Guo; Steve S. Chung

doi:10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory

J. P. Wu, M. Y. Lee, T. C. Kao, Y. J. Li, C. H. Liu, J. C. Guo, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 105 cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28μ W of the power at Vcc = 0.8V, and very small area size of 10-5 mm2. It is well-suited for the energy-efficient AI-Inference in CIM.

Original language	English
Title of host publication	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350334166
DOIs	https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139
State	Published - 2023
Event	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan Duration: 17 Apr 2023 → 20 Apr 2023

Publication series

Name	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Country/Territory	Taiwan
City	Hsinchu
Period	17/04/23 → 20/04/23

Access to Document

10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

Cite this

Wu, J. P., Lee, M. Y., Kao, T. C., Li, Y. J., Liu, C. H., Guo, J. C., & Chung, S. S. (2023). An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory. In 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

Wu, J. P. ; Lee, M. Y. ; Kao, T. C. et al. / An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

@inproceedings{a8ababca8e8048338574fb11cab5bebc,

title = "An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory",

abstract = "In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 105 cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28μ W of the power at Vcc = 0.8V, and very small area size of 10-5 mm2. It is well-suited for the energy-efficient AI-Inference in CIM.",

author = "Wu, {J. P.} and Lee, {M. Y.} and Kao, {T. C.} and Li, {Y. J.} and Liu, {C. H.} and Guo, {J. C.} and Chung, {Steve S.}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 ; Conference date: 17-04-2023 Through 20-04-2023",

year = "2023",

doi = "10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139",

language = "English",

series = "2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings",

address = "美國",

}

Wu, JP, Lee, MY, Kao, TC, Li, YJ, Liu, CH, Guo, JC & Chung, SS 2023, An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory. in 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023, Hsinchu, Taiwan, 17/04/23. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory. / Wu, J. P.; Lee, M. Y.; Kao, T. C. et al.
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory

AU - Wu, J. P.

AU - Lee, M. Y.

AU - Kao, T. C.

AU - Li, Y. J.

AU - Liu, C. H.

AU - Guo, J. C.

AU - Chung, Steve S.

PY - 2023

Y1 - 2023

N2 - In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 105 cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28μ W of the power at Vcc = 0.8V, and very small area size of 10-5 mm2. It is well-suited for the energy-efficient AI-Inference in CIM.

AB - In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 105 cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28μ W of the power at Vcc = 0.8V, and very small area size of 10-5 mm2. It is well-suited for the energy-efficient AI-Inference in CIM.

UR - http://www.scopus.com/inward/record.url?scp=85162997643&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

M3 - Conference contribution

AN - SCOPUS:85162997643

T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023

Y2 - 17 April 2023 through 20 April 2023

ER -

Wu JP, Lee MY, Kao TC, Li YJ, Liu CH, Guo JC et al. An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory. In 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134139

An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this