An all-digital phase-locked loop with a multi-delay-switching TDC

Keyphrases

• Digital Converter 100%
• All-digital Phase-locked Loop (ADPLL) 100%
• Multiple Delays 100%
• Low Power 66%
• Switching Mechanism 66%
• CMOS Process 33%
• Time-to-digital Converter 33%
• Low Power Dissipation 33%
• Low Area 33%
• 0.18-μm CMOS Technology 33%
• Whole Systems 33%
• Active Area 33%
• Peak-to-peak Jitter 33%
• Area Occupation 33%
• Converter Design 33%

Engineering

• Digital Converter 100%
• Phase Locked Loop 100%
• Energy Dissipation 33%
• Active Area 33%