@inproceedings{d815e87aaf2243e099a83d8b4e56de47,
title = "An all-digital phase-locked loop with a multi-delay-switching TDC",
abstract = "This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 MHz. The design has been implemented in 0.18 um CMOS process with an active area of 0.1088 mm2 and the whole system consumes 8.41 mW at 800 MHz.",
author = "Su, {Chung Cheng} and Cheng-Chung Lin and Chung-Chih Hung",
year = "2017",
month = jun,
day = "5",
doi = "10.1109/VLSI-DAT.2017.7939662",
language = "English",
series = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",
address = "美國",
note = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 ; Conference date: 24-04-2017 Through 27-04-2017",
}