An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Geng Cing Lin; Shao Cheng Wang; Yi Wei Lin; Ming Chien Tsai; Ching Te Chuang; Shyh-Jye Jou; Nan Chun Lien; Wei Chiang Shih; Kuen Di Lee; Jyun Kai Chu

doi:10.1109/ISCAS.2012.6271804

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Geng Cing Lin^*, Shao Cheng Wang, Yi Wei Lin, Ming Chien Tsai, Ching Te Chuang, Shyh-Jye Jou, Nan Chun Lien, Wei Chiang Shih, Kuen Di Lee, Jyun Kai Chu

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V _TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V _TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.

Original language	English
Pages	2485-2488
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271804
State	Published - 28 Sep 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

Access to Document

10.1109/ISCAS.2012.6271804

Cite this

Lin, G. C., Wang, S. C., Lin, Y. W., Tsai, M. C., Chuang, C. T., Jou, S.-J., Lien, N. C., Shih, W. C., Lee, K. D., & Chu, J. K. (2012). An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. 2485-2488. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271804

@conference{46aef7df9b23492dbc8a58ace869b66a,

title = "An all-digital bit transistor characterization scheme for CMOS 6T SRAM array",

abstract = " We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.",

author = "Lin, {Geng Cing} and Wang, {Shao Cheng} and Lin, {Yi Wei} and Tsai, {Ming Chien} and Chuang, {Ching Te} and Shyh-Jye Jou and Lien, {Nan Chun} and Shih, {Wei Chiang} and Lee, {Kuen Di} and Chu, {Jyun Kai}",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/ISCAS.2012.6271804",

language = "English",

pages = "2485--2488",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

Lin, GC, Wang, SC, Lin, YW, Tsai, MC, Chuang, CT, Jou, S-J, Lien, NC, Shih, WC, Lee, KD & Chu, JK 2012, 'An all-digital bit transistor characterization scheme for CMOS 6T SRAM array', Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/05/12 - 23/05/12 pp. 2485-2488. https://doi.org/10.1109/ISCAS.2012.6271804

TY - CONF

T1 - An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

AU - Lin, Geng Cing

AU - Wang, Shao Cheng

AU - Lin, Yi Wei

AU - Tsai, Ming Chien

AU - Chuang, Ching Te

AU - Jou, Shyh-Jye

AU - Lien, Nan Chun

AU - Shih, Wei Chiang

AU - Lee, Kuen Di

AU - Chu, Jyun Kai

PY - 2012/9/28

Y1 - 2012/9/28

N2 - We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.

AB - We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.

UR - http://www.scopus.com/inward/record.url?scp=84866601820&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271804

DO - 10.1109/ISCAS.2012.6271804

M3 - Paper

AN - SCOPUS:84866601820

SP - 2485

EP - 2488

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this