An 8 Gbps, 4:1 transition-aware self-toggling multiplexer

Wei-Zen Chen, Yi Hung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Qb delay enables high speed multiplexing. Power reduction can be achieved by deactivating the power hungry flip-flop thanks to the random probability of data transition. Fabricated in 55 nm CMOS technology, the core circuit occupies a chip area of 77 × 81μm2 only. It dissipates 10.3 mW from a 1.2 V supply.

Original languageEnglish
Title of host publication2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages659-662
Number of pages4
EditionFebruary
ISBN (Electronic)9781479952304
DOIs
StatePublished - 5 Feb 2015
Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
Duration: 17 Nov 201420 Nov 2014

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
NumberFebruary
Volume2015-February

Conference

Conference2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Country/TerritoryJapan
CityIshigaki Island, Okinawa
Period17/11/1420/11/14

Keywords

  • TSPC
  • clock gating
  • dynamic flip flop
  • multiplexer

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