An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

Bo Wei Chen; Yung Hui Chung; Chia-Ming Tsai

doi:10.1109/VLSI-DAT52063.2021.9427312

An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

Bo Wei Chen, Yung Hui Chung, Chia-Ming Tsai

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper presents an 8-bit 1.25GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5dB and 43.4dB, respectively. When split-then-share buffer turns on, ERBW achieves up to 2.5 GHz within ±1dB bandwidth flatness. Peak DNL and INL are 0.71LSB and 0.72LSB, respectively. Setting at error magnitude of 4LSB and 32LSB, the bit error rate (BER) can achieve 5.4×10-6 and 5×10-10 errors/conversion, respectively. The ADC core consumes 20mW at 1.2V supply and occupies an active area of 0.14mm2.

Original language	American English
DOIs	https://doi.org/10.1109/VLSI-DAT52063.2021.9427312
State	Published - 19 Apr 2021
Event	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan Duration: 19 Apr 2021 → 22 Apr 2021

Conference

Conference	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
Country/Territory	Taiwan
City	Hsinchu
Period	19/04/21 → 22/04/21

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10.1109/VLSI-DAT52063.2021.9427312

Cite this

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title = "An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique",

abstract = "This paper presents an 8-bit 1.25GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5dB and 43.4dB, respectively. When split-then-share buffer turns on, ERBW achieves up to 2.5 GHz within ±1dB bandwidth flatness. Peak DNL and INL are 0.71LSB and 0.72LSB, respectively. Setting at error magnitude of 4LSB and 32LSB, the bit error rate (BER) can achieve 5.4×10-6 and 5×10-10 errors/conversion, respectively. The ADC core consumes 20mW at 1.2V supply and occupies an active area of 0.14mm2. ",

author = "Chen, {Bo Wei} and Chung, {Yung Hui} and Chia-Ming Tsai",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 ; Conference date: 19-04-2021 Through 22-04-2021",

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doi = "10.1109/VLSI-DAT52063.2021.9427312",

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AU - Chung, Yung Hui

AU - Tsai, Chia-Ming

PY - 2021/4/19

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N2 - This paper presents an 8-bit 1.25GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5dB and 43.4dB, respectively. When split-then-share buffer turns on, ERBW achieves up to 2.5 GHz within ±1dB bandwidth flatness. Peak DNL and INL are 0.71LSB and 0.72LSB, respectively. Setting at error magnitude of 4LSB and 32LSB, the bit error rate (BER) can achieve 5.4×10-6 and 5×10-10 errors/conversion, respectively. The ADC core consumes 20mW at 1.2V supply and occupies an active area of 0.14mm2.

AB - This paper presents an 8-bit 1.25GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5dB and 43.4dB, respectively. When split-then-share buffer turns on, ERBW achieves up to 2.5 GHz within ±1dB bandwidth flatness. Peak DNL and INL are 0.71LSB and 0.72LSB, respectively. Setting at error magnitude of 4LSB and 32LSB, the bit error rate (BER) can achieve 5.4×10-6 and 5×10-10 errors/conversion, respectively. The ADC core consumes 20mW at 1.2V supply and occupies an active area of 0.14mm2.

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U2 - 10.1109/VLSI-DAT52063.2021.9427312

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M3 - Paper

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T2 - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021

Y2 - 19 April 2021 through 22 April 2021

ER -

An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

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