An 8μW 100kS/s successive approximation ADC for biomedical applications

Yung Jui Chen; Kea Tiong Tang; Wai-Chi  Fang

doi:10.1109/LISSA.2009.4906739

An 8μW 100kS/s successive approximation ADC for biomedical applications

Yung Jui Chen^*, Kea Tiong Tang, Wai-Chi Fang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-μm standard CMOS technology and operates at low supply voltage at 1V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of 53dB for supply voltage of 1V, at sampling rate of 100kS/s and power consumption of 8μW.

Original language	English
Title of host publication	2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009
Pages	176-178
Number of pages	3
DOIs	https://doi.org/10.1109/LISSA.2009.4906739
State	Published - 23 Jul 2009
Event	2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009 - Bethesda, MD, United States Duration: 9 Apr 2009 → 10 Apr 2009

Publication series

Name	2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009

Conference

Conference	2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009
Country/Territory	United States
City	Bethesda, MD
Period	9/04/09 → 10/04/09

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10.1109/LISSA.2009.4906739

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@inproceedings{3d2f283b1e5c4de69cef9888ed88068e,

title = "An 8μW 100kS/s successive approximation ADC for biomedical applications",

abstract = "A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-μm standard CMOS technology and operates at low supply voltage at 1V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of 53dB for supply voltage of 1V, at sampling rate of 100kS/s and power consumption of 8μW.",

author = "Chen, {Yung Jui} and Tang, {Kea Tiong} and Wai-Chi Fang",

year = "2009",

month = jul,

day = "23",

doi = "10.1109/LISSA.2009.4906739",

language = "English",

isbn = "9781424442935",

series = "2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009",

pages = "176--178",

booktitle = "2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009",

note = "2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009 ; Conference date: 09-04-2009 Through 10-04-2009",

}

Chen, YJ, Tang, KT & Fang, W-C 2009, An 8μW 100kS/s successive approximation ADC for biomedical applications. in 2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009., 4906739, 2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009, pp. 176-178, 2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009, Bethesda, MD, United States, 9/04/09. https://doi.org/10.1109/LISSA.2009.4906739

An 8μW 100kS/s successive approximation ADC for biomedical applications. / Chen, Yung Jui; Tang, Kea Tiong; Fang, Wai-Chi .
2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009. 2009. p. 176-178 4906739 (2009 IEEE/NIH Life Science Systems and Applications Workshop, LiSSA 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-μm standard CMOS technology and operates at low supply voltage at 1V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of 53dB for supply voltage of 1V, at sampling rate of 100kS/s and power consumption of 8μW.

AB - A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-μm standard CMOS technology and operates at low supply voltage at 1V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of 53dB for supply voltage of 1V, at sampling rate of 100kS/s and power consumption of 8μW.

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Y2 - 9 April 2009 through 10 April 2009

ER -

An 8μW 100kS/s successive approximation ADC for biomedical applications

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