@inproceedings{242cc22b39d849adbd33b387acbf42ea,
title = "An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications",
abstract = "A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.",
keywords = "CIFAR-10, Co-Training, Computing In-Memory, In-RRAM Computing",
author = "Chi Liu and Li, \{Shao Tzu\} and Pan, \{Tong Lin\} and Ni, \{Cheng En\} and Yun Sung and Hu, \{Chia Lin\} and Chang, \{Kang Yu\} and Hou, \{Tuo Hung\} and Chang, \{Tian Sheuan\} and Jou, \{Shyh Jye\}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 ; Conference date: 18-04-2022 Through 21-04-2022",
year = "2022",
doi = "10.1109/VLSI-DAT54769.2022.9768058",
language = "English",
series = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",
address = "美國",
}