All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

Yi Ping Kuo; Po-Tsang Huang; Chung Shiang Wu; Yu Jie Liang; Ching Te Chuang; Yuan Hua Chu; Wei Hwang

doi:10.1109/VLSI-DAT.2015.7114514

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

Yi Ping Kuo, Po-Tsang Huang, Chung Shiang Wu, Yu Jie Liang, Ching Te Chuang, Yuan Hua Chu, Wei Hwang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114514
State	Published - 28 May 2015
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	27/04/15 → 29/04/15

Access to Document

10.1109/VLSI-DAT.2015.7114514

Cite this

Kuo, Y. P., Huang, P.-T., Wu, C. S., Liang, Y. J., Chuang, C. T., Chu, Y. H., & Hwang, W. (2015). All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 Article 7114514 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114514

Kuo, Yi Ping ; Huang, Po-Tsang ; Wu, Chung Shiang et al. / All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

@inproceedings{185fdd59beb24e8985ba2549ba1a967d,

title = "All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction",

abstract = "In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.",

author = "Kuo, {Yi Ping} and Po-Tsang Huang and Wu, {Chung Shiang} and Liang, {Yu Jie} and Chuang, {Ching Te} and Chu, {Yuan Hua} and Wei Hwang",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114514",

language = "English",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

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note = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

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Kuo, YP, Huang, P-T, Wu, CS, Liang, YJ, Chuang, CT, Chu, YH & Hwang, W 2015, All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114514, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114514

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. / Kuo, Yi Ping; Huang, Po-Tsang; Wu, Chung Shiang et al.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114514 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kuo, Yi Ping

AU - Huang, Po-Tsang

AU - Wu, Chung Shiang

AU - Liang, Yu Jie

AU - Chuang, Ching Te

AU - Chu, Yuan Hua

AU - Hwang, Wei

PY - 2015/5/28

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N2 - In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.

AB - In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.

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Kuo YP, Huang PT, Wu CS, Liang YJ, Chuang CT, Chu YH et al. All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7114514. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). doi: 10.1109/VLSI-DAT.2015.7114514

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

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