All digital phase-locked loop with modified binary search of frequency acquisition

Shyh-Jye Jou; Ya Lan Tsao; I. Ying Yang

doi:10.1109/ICECS.1998.814861

All digital phase-locked loop with modified binary search of frequency acquisition

Shyh-Jye Jou^*, Ya Lan Tsao, I. Ying Yang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm².

Original language	English
Pages	195-198
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.1998.814861
State	Published - 1 Dec 1998
Event	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal Duration: 7 Sep 1998 → 10 Sep 1998

Conference

Conference	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
City	Lisboa, Portugal
Period	7/09/98 → 10/09/98

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10.1109/ICECS.1998.814861

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Jou, S.-J., Tsao, Y. L., & Yang, I. Y. (1998). All digital phase-locked loop with modified binary search of frequency acquisition. 195-198. Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal. https://doi.org/10.1109/ICECS.1998.814861

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abstract = "In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2.",

author = "Shyh-Jye Jou and Tsao, {Ya Lan} and Yang, {I. Ying}",

year = "1998",

month = dec,

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doi = "10.1109/ICECS.1998.814861",

language = "English",

pages = "195--198",

note = "Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology ; Conference date: 07-09-1998 Through 10-09-1998",

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Jou, S-J, Tsao, YL & Yang, IY 1998, 'All digital phase-locked loop with modified binary search of frequency acquisition', Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal, 7/09/98 - 10/09/98 pp. 195-198. https://doi.org/10.1109/ICECS.1998.814861

All digital phase-locked loop with modified binary search of frequency acquisition. / Jou, Shyh-Jye; Tsao, Ya Lan; Yang, I. Ying.
1998. 195-198 Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal.

Research output: Contribution to conference › Paper › peer-review

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AB - In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2.

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All digital phase-locked loop with modified binary search of frequency acquisition

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